AT89C51RD2Qualification Methodology

　　All product qualifications are split into three distinct steps as shown below. Before a product is released for use,successful qualification testing are required at wafer, device and package level Wafer Level Reliability consists in testing individually basic process modules regarding their well known potential limitations (Electro-migration, Hot Carriers Injection, Oxide Breakdown, NVM Data Retention).Each test is performed using wafer process specific structures.Device reliability is covering either dice design and processing aspects. The tests are performed on deviceunder qualification, but generic data may also be considered for reliability calculation.For each package type proposed in the Datasheet, it is verified that qualification data are available. If not qualification tests are carried out for the new package types. In addition, one package type is selected to verify packaging reliability of the device under qualification.

　　AT89C51RD2Test conditions

　　The test is performed by forcing a high drain bias on the test device (Vds>Vddmax) to accelerate the carriers to the maximum. At the same time the gate bias (Vgs) is chosen in order to maximize the injection of carriers into the gate oxide and also the substrate. WLR_B n-channel W/L 0.35um/25um the stress is performed on a number of transistors, each at a different stress condition Vds,stress and Vgs,stress. For each transistor, the time to reach the failure criteria (dIdsat/Idsat=10%) is obtained. NMOS is more sensitive to hot carriers compared to PMOS.Consequently NMOS is the only structure tested.

    AT89C51RD2索引

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